I am looking for possibilities to integrate VSD with other tools, mainly for computation/analysis/simulation. My objectives would be:
– to perform trade-off studies
– to import/export models from/to Simulink or Modelica
In the first case, I saw that other MBSE tools are capable of interacting with Parametric Constraint Evaluators, calculating the values required to perform a trade-off study. Measures of effectiveness, weights and alternatives are defined in the system model, and the output is returned from the PCE to the system model. Is it possible to do something similar in VSD?
In the second case, I would like to create models in SSDE which are then exported to Simulink/Modelica and used to perform simulations. Alternatively, blocks created in Simulink/Modelica can be imported in SSDE and integrated in the system model. I saw that some solve this issue by using specific SysML stereotypes like <<SimulinkBlock>>, is it possible to do it also in VSD?